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ltc236 4 -16 1 236416fa 16-bit, 250ksps, pseudo- differential unipolar sar adc with 94.7db snr typical application features description the lt c ? 2364-16 is a low noise, low power, high speed 16-bit successive approximation register ( sar) adc. operating from a 2.5 v supply, the ltc2364-16 has a 0 v to v ref pseudo-differential unipolar input range with v ref ranging from 2.5 v to 5.1 v. the ltc2364-16 consumes only 3.4 mw and achieves 0.75 lsb inl maximum, no missing codes at 16 bits with 94.7db snr. the ltc2364-16 has a high speed spi-compatible serial interface that supports 1.8 v , 2.5 v , 3.3 v and 5 v logic while also featuring a daisy-chain mode. the fast 250 ksps throughput with no cycle latency makes the ltc2364-16 ideally suited for a wide variety of high speed applications. an internal oscillator sets the conversion time, easing exter - nal timing considerations. the ltc2364-16 automatically powers down between conversions, leading to reduced power dissipation that scales with the sampling rate. 32k point fft f s = 250ksps, f in = 2khz applications n 250ksps throughput rate n 0.75lsb inl (max) n guaranteed 16-bit no missing codes n low power: 3.4mw at 250ksps, 3.4w at 250sps n 94.7db snr ( typ ) at f in = 2khz n C 120db thd ( typ ) at f in = 2khz n guaranteed operation to 125c n 2.5 v supply n pseudo-differential unipolar input range: 0v to v ref n v ref input range from 2.5v to 5.1v n no pipeline delay, no cycle latency n 1.8 v to 5v i/o voltages n spi-compatible serial i/o with daisy-chain mode n internal conversion clock n 16- lead msop and 4mm 3mm dfn packages n medical imaging n high speed data acquisition n portable or compact instrumentation n industrial process control n low power battery-operated instrumentation n ate l , lt , lt c , lt m , linear technology and the linear logo are registered trademarks and softspan is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7705765. 10 v ref 0v 10nf C + sample clock 236416 ta01a 10f 0.1f 2.5v ref 1.8v to 5v 2.5v to 5.1v 47f(x5r, 0805 size) ref gnd chain rdl/sdi sdo sck busy cnv ltc2364-16 lt ? 6202 v dd ov dd in + in C frequency (khz) 0 25 50 75 100 125 C180 amplitude (dbfs) C60 C40 C20C80 C100C120 C140 C160 0 236416 ta01b snr = 94.7dbthd = C121db sinad = 94.7db sfdr = 125db downloaded from: http:///
ltc236 4 -16 2 236416fa pin configuration absolute maximum ratings supply voltage (v dd ) ............................................... 2.8 v supply voltage ( ov dd ) ................................................ 6v reference input ( ref ) ................................................. 6v analog input voltage ( note 3) in + , in C ......................... ( gnd C 0.3 v) to ( ref + 0.3 v) digital input voltage ( note 3) .......................... ( gnd C 0.3 v) to ( ov dd + 0.3 v) digital output voltage ( note 3) .......................... ( gnd C 0.3 v) to ( ov dd + 0.3 v) (notes 1, 2) 1615 14 13 12 11 10 9 17 gnd 12 3 4 5 6 7 8 gndov dd sdosck rdl/sdi busy gnd cnv chain v dd gnd in + in C gnd refref top view de package 16-lead (4mm 3mm) plastic dfn t jmax = 150c, ja = 40c/w exposed pad (pin 17) is gnd, must be soldered to pcb 12 3 4 5 6 7 8 chain v dd gnd in + in C gnd refref 1615 14 13 12 11 10 9 gndov dd sdosck rdl/sdi busy gnd cnv top view ms package 16-lead plastic msop t jmax = 150c, ja = 110c/w order information lead free finish tape and reel part marking* package description temperature range ltc2364cms-16#pbf ltc2364cms-16#trpbf 236416 16-lead plastic msop 0c to 70c ltc2364ims-16#pbf ltc2364ims-16#trpbf 236416 16-lead plastic msop C40c to 85c ltc2364hms-16#pbf ltc2364hms-16#trpbf 236416 16-lead plastic msop C40c to 125c ltc2364cde-16#pbf ltc2364cde-16#trpbf 23646 16-lead (4mm 3mm) plastic dfn 0c to 70c ltc2364ide-16#pbf ltc2364ide-16#trpbf 23646 16-lead (4mm 3mm) plastic dfn C40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container . consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ power dissipation .............................................. 500 mw operating temperature range ltc 2364 c ................................................ 0 c to 70 c ltc 2364 i ............................................. C40 c to 85 c ltc 2364 h .......................................... C40 c to 125 c storage temperature range .................. C65 c to 150 c downloaded from: http:///
ltc236 4 -16 3 236416fa dynamic accuracy symbol parameter conditions min typ max units sinad signal-to-(noise + distortion) ratio f in = 2khz, v ref = 5v l 91.9 94.7 db f in = 2khz, v ref = 5v, (h-grade) l 91.7 94.7 db snr signal-to-noise ratio f in = 2khz, v ref = 5v f in = 2khz, v ref = 2.5v l l 92.5 87.7 94.7 90.7 db db f in = 2khz, v ref = 5v, (h-grade) f in = 2khz, v ref = 2.5v, (h-grade) l l 92.2 87.3 94.7 90.7 db db thd total harmonic distortion f in = 2khz, v ref = 5v f in = 2khz, v ref = 2.5v l l C120 C120 C102 C102 db db sfdr spurious free dynamic range f in = 2khz, v ref = 5v l 103 122 db C3db input bandwidth 34 mhz aperture delay 500 ps aperture jitter 4 ps transient response full-scale step 3.46 s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and a in = C1dbfs. (notes 4, 8) electrical characteristics symbol parameter conditions min typ max units v in + absolute input range (in + ) (note 5) l C0.1 v ref + 0.1 v v in C absolute input range (in C ) (note 5) l C0.1 0.1 v v in + C v in C input differential voltage range v in = v in + C v in C l 0 v ref v i in analog input leakage current l 1 a c in analog input capacitance sample mode hold mode 45 5 pf pf cmrr input common mode rejection ratio f in = 125khz 80 db the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) converter characteristics symbol parameter conditions min typ max units resolution l 16 bits no missing codes l 16 bits transition noise 0.5 lsb rms inl integral linearity error (note 6) l C0.75 0.1 0.75 lsb dnl differential linearity error l C0.5 0.1 0.5 lsb zse zero-scale error (note 7) l C4 0 4 lsb zero-scale error drift 4 mlsb/c fse full-scale error (note 7) l C20 2 20 lsb full-scale error drift 0.1 ppm/c the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) downloaded from: http:///
ltc236 4 -16 4 236416fa reference input symbol parameter conditions min typ max units v ref reference voltage (note 5) l 2.5 5.1 v i ref reference input current (note 9) l 0.12 0.2 ma the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) digital inputs and digital outputs symbol parameter conditions min typ max units v ih high level input voltage l 0.8 ? ov dd v v il low level input voltage l 0.2 ? ov dd v i in digital input current v in = 0v to ov dd l C10 10 a c in digital input capacitance 5 pf v oh high level output voltage i o = C500a l ov dd C 0.2 v v ol low level output voltage i o = 500a l 0.2 v i oz hi-z output leakage current v out = 0v to ov dd l C10 10 a i source output source current v out = 0v C10 ma i sink output sink current v out = ov dd 10 ma the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) adc timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) power requirements symbol parameter conditions min typ max units v dd supply voltage l 2.375 2.5 2.625 v ov dd supply voltage l 1.71 5.25 v i vdd i ovdd i pd i pd supply current supply current power down mode power down mode 250ksps sample rate 250ksps sample rate (c l = 20pf) conversion done (i vdd + i ovdd + i ref , v ref > 2v) conversion done (i vdd + i ovdd + i ref , v ref > 2v, h-grade) l l l 1.36 0.1 0.9 0.9 1.7 90 140 ma ma a a p d power dissipation power down mode power down mode 250ksps sample rate conversion done (i vdd + i ovdd + i ref , v ref > 2v) conversion done (i vdd + i ovdd + i ref , v ref > 2v, h-grade) 3.4 2.25 2.25 4.25 225 315 mw w w the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) symbol parameter conditions min typ max units f smpl maximum sampling frequency l 250 ksps t conv conversion time l 1.9 3 s t acq acquisition time t acq = t cyc C t hold (note 10) l 3.460 s t hold maximum time between acquisitions l 540 ns t cyc time between conversions l 4 s t cnvh cnv high time l 20 ns t busylh cnv to busy delay c l = 20pf l 13 ns t cnvl minimum low time for cnv (note 11) l 20 ns t quiet sck quiet time from cnv (note 10) l 20 ns downloaded from: http:///
ltc236 4 -16 5 236416fa adc timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may effect device reliability and lifetime. note 2: all voltage values are with respect to ground. note 3: when these pin voltages are taken below ground or above ref or ov dd , they will be clamped by internal diodes. this product can handle input currents up to 100ma below ground or above ref or ov dd without latch-up.note 4: v dd = 2.5v, ov dd = 2.5v, ref = 5v, f smpl = 250khz. note 5: recommended operating conditions. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: zero-scale error is the offset voltage measured from 0.5lsb when the output code flickers between 0000 0000 0000 0000 and 0000 0000 0000 0001. full-scale error is the deviation of the last code transition from ideal and includes the effect of offset error. note 8: all specifications in db are referred to a full-scale 5v input with a 5v reference voltage.note 9: f smpl = 250khz, i ref varies proportionately with sample rate. note 10: guaranteed by design, not subject to test. note 11: parameter tested and guaranteed at ov dd = 1.71v, ov dd = 2.5v and ov dd = 5.25v. note 12: t sck of 10ns maximum allows a shift clock frequency up to 100mhz for rising capture. figure 1. voltage levels for timing specifications symbol parameter conditions min typ max units t sck sck period (notes 11, 12) l 10 ns t sckh sck high time l 4 ns t sckl sck low time l 4 ns t ssdisck sdi setup time from sck (note 11) l 4 ns t hsdisck sdi hold time from sck (note 11) l 1 ns t sckch sck period in chain mode t sckch = t ssdisck + t dsdo (note 11) l 13.5 ns t dsdo sdo data valid delay from sck c l = 20pf (note 11) l 9.5 ns t hsdo sdo data remains valid delay from sck c l = 20pf (note 10) l 1 ns t dsdobusyl sdo data valid delay from busy c l = 20pf (note 10) l 5 ns t en bus enable time after rdl (note 11) l 16 ns t dis bus relinquish time after rdl (note 11) l 13 ns 0.8*ov dd 0.2*ov dd 50% 50% 236416 f01 0.2*ov dd 0.8*ov dd 0.2*ov dd 0.8*ov dd t delay t width t delay downloaded from: http:///
ltc236 4 -16 6 236416fa typical performance characteristics 32k point fft f s = 250ksps, f in = 2khz snr, sinad vs input frequency thd, harmonics vs input frequency snr, sinad vs input level, f in = 2khz snr, sinad vs reference voltage, f in = 2khz thd, harmonics vs reference voltage, f in = 2khz integral nonlinearity vs output code differential nonlinearity vs output code dc histogram t a = 25c, v dd = 2.5v, ov dd = 2.5v, ref = 5v, f smpl = 250ksps, unless otherwise noted. output code 0 16384 32768 49152 65536 C1.0 inl error (lsb) 0.0 0.40.2 0.6 0.8 C0.2C0.4 C0.8 C0.6 1.0 236416 g01 output code C0.5 dnl error (lsb) 0.40.3 0.2 0.1 0.0 C0.4 C0.3 C0.2 C0.1 0.5 236416 g02 0 16384 32768 49152 65536 code 32676 0 counts 20000 30000 40000 50000 60000 70000 32677 32678 236416 g03 80000 90000 100000 = 0.5 10000 32679 32680 frequency (khz) 0 25 50 75 100 125 C180 amplitude (dbfs) C60 C40 C20C80 C100C120 C140 C160 0 236416 g04 snr = 94.7dbthd = C121db sinad = 94.7db sfdr = 125db frequency (khz) 0 75 50 25 100 125 70 snr, sinad (dbfs) 8580 75 100 snr sinad 9590 236416 g05 frequency (khz) 0 C160 harmonics, thd (dbfs) C150 C130 C120 C110 C60 thd 2nd 3rd C90 50 100 236416 g06 C140 C80 C70 C100 25 75 125 input level (db) C40 93.0 snr, sinad (dbfs) 93.5 94.0 94.5 95.0 sinad 96.0 95.5 C30 C20 C10 0 236416 g07 snr reference voltage (v) 2.5 93 94 95 snr sinad 4.5 236416 g08 9291 3 3.5 4 5 90 snr, sinad (dbfs) reference voltage (v) 2.5 harmonics, thd (dbfs) C120 C110 3rd C100 4.5 236416 g09 C130C140 C125 C115 C105C135 C145 C150 3 3.5 4 5 2nd thd downloaded from: http:///
ltc236 4 -16 7 236416fa snr, sinad vs temperature, f in = 2khz thd, harmonics vs temperature, f in = 2khz typical performance characteristics supply current vs temperature shutdown current vs temperature cmrr vs input frequency reference current vs reference voltage inl/dnl vs temperature full-scale error vs temperature offset error vs temperature t a = 25c, v dd = 2.5v, ov dd = 2.5v, ref = 5v, f smpl = 250ksps, unless otherwise noted. temperature (c) C55 snr, sinad (dbfs) 94.0 94.5 95.0 105 236416 g10 93.593.0 C15 25 65 C35 125 5 45 85 96.0 95.5 snr sinad temperature (c) C55 C145 harmonics, thd (dbfs) C140 C130 C125 C120 C110 C35 45 85 236416 g11 C135 C115 25 125 C15 5 65 105 3rd 2nd thd temperature (c) C55 C1.0 inl/dnl error (lsb) C0.5 0 0.5 1.0 C35 C15 5 25 236416 g12 45 65 85 105 125 max dnl min dnl min inl max inl temperature (c) C55 C10 full-scale error (lsb) C2C4 C6 C8 0 64 2 10 8 C35 C15 5 25 236416 g13 45 65 85 105 125 temperature (c) C55 offset error (lsb) C4 C2 2 0 C15 25 45 125 236416 g14 C35 5 65 85 105 4 C3 1 C1 3 temperature (c) C55 power supply current (ma) 0.8 1.0 105 236416 g15 0.6 0.4 0 C15 25 65 C35 125 5 45 85 0.2 1.41.2 i vdd i ref i ovdd temperature (c) power-down current (a) 45 4035 30 236416 g16 0 5 10 15 20 25 C55 C35 C15 5 25 45 65 85 105 125 i vdd + i ovdd + i ref frequency (khz) 0 75 50 25 100 125 70 cmrr (db) 8580 75 100 9590 236416 g17 reference voltage (v) 2.5 0 reference current (ma) 0.05 3.5 4.5 5 0.20 0.15 236416 g18 3 4 0.10 downloaded from: http:///
ltc236 4 -16 8 236416fa chain ( pin 1): chain mode selector pin. when low, the ltc2364-16 operates in normal mode and the rdl/sdi input pin functions to enable or disable sdo. when high, the ltc2364-16 operates in chain mode and the rdl/sdi pin functions as sdi, the daisy-chain serial data input. logic levels are determined by ov dd . v dd ( pin 2): 2.5 v power supply. the range of v dd is 2.375v to 2.625 v. bypass v dd to gnd with a 10 f ceramic capacitor. gnd (pins 3, 6, 10 and 16): ground. in + ( pin 4): analog input. in + operates differential with respect to in C with an in + -in C range of 0v to v ref . in C ( pin 5): analog ground sense. in C has an input range of 100 mv with respect to gnd and must be tied to the ground plane or a remote ground sense. ref ( pins 7, 8): reference inputs. the range of ref is 2.5 v to 5.1 v. this pin is referred to the gnd pin and should be decoupled closely to the pin with a 47 f ceramic capacitor (x5r, 0805 size).cnv ( pin 9): convert input. a rising edge on this input powers up the part and initiates a new conversion. logic levels are determined by ov dd . busy ( pin 11): busy indicator. goes high at the start of a new conversion and returns low when the conversion has finished. logic levels are determined by ov dd . rdl/sdi ( pin 12): when chain is low, the part is in nor- mal mode and the pin is treated as a bus enabling input. when chain is high, the part is in chain mode and the pin is treated as a serial data input pin where data from another adc in the daisy chain is input. logic levels are determined by ov dd . sck ( pin 13): serial data clock input. when sdo is enabled , the conversion result or daisy-chain data from another adc is shifted out on the rising edges of this clock msb first. logic levels are determined by ov dd . sdo ( pin 14): serial data output. the conversion result or daisy-chain data is output on this pin on each rising edge of sck msb first. the output data is in straight binary format. logic levels are determined by ov dd . ov dd ( pin 15): i/o interface digital power. the range of ov dd is 1.71 v to 5.25 v. this supply is nominally set to the same supply as the host interface (1.8 v , 2.5 v , 3.3 v, or 5v). bypass ov dd to gnd with a 0.1f capacitor. gnd ( exposed pad pin 17, dfn package only): ground. exposed pad must be soldered directly to the ground plane . pin functions downloaded from: http:///
ltc236 4 -16 9 236416fa functional block diagram timing diagram conversion timing using the serial interface ref = 5v in + v dd = 2.5v ov dd = 1.8v to 5v in C chaincnv gnd busy sdosck rdl/sdi control logic 16-bit sampling adc spi port +C 236416 bd power-down convert acquire hold d13 d15 d14 d2 d1 d0 sdo sck cnv chain, rdl/sdi = 0 busy 236416 td01 downloaded from: http:///
ltc236 4 -16 10 236416fa overview the ltc2364-16 is a low noise, low power, high speed 16-bit successive approximation register ( sar) adc. operating from a single 2.5 v supply, the ltc2364-16 supports a 0 v to v ref pseudo-differential unipolar input range with v ref ranging from 2.5 v to 5.1 v, making it ideal for high performance applications which require a wide dynamic range. the ltc2364-16 achieves 0.75 lsb inl max, no missing codes at 16 bits and 94.7db snr. fast 250 ksps throughput with no cycle latency makes the ltc2364-16 ideally suited for a wide variety of high speed applications. an internal oscillator sets the con- version time, easing external timing considerations. the ltc2364-16 dissipates only 3.4 mw at 250 ksps, while an auto power-down feature is provided to further reduce power dissipation during inactive periods. converter operation the ltc2364-16 operates in two phases. during the ac- quisition phase, the charge redistribution capacitor d/a converter ( cdac) is connected to the in + and in C pins to sample the pseudo-differential analog input voltage. a ris- ing edge on the cnv pin initiates a conversion. during the conversion phase, the 16- bit cdac is sequenced through a successive approximation algorithm, effectively comparing the sampled input with binary-weighted fractions of the reference voltage ( e.g . v ref /2, v ref /4 v ref /65536) using the differential comparator. at the end of conversion, the cdac output approximates the sampled analog input. the adc control logic then prepares the 16- bit digital output code for serial transfer. transfer function the ltc2364-16 digitizes the full-scale voltage of ref into 2 16 levels, resulting in an lsb size of 76 v with ref = 5 v. the ideal transfer function is shown in figure ?2. the output data is in straight binary format. applications information figure 2. ltc2364-16 transfer function figure 3. the equivalent circuit for the differential analog input of the ltc2364-16 analog input the analog inputs of the ltc2364-16 are pseudo-differen- tial in order to reduce any unwanted signal that is common to both inputs. the analog inputs can be modeled by the equivalent circuit shown in figure 3. the diodes at the input provide esd protection. in the acquisition phase, each input sees approximately 45 pf ( c in ) from the sampling cdac in series with 40 ( r on ) from the on-resistance of the sampling switch. the in + input draws a current spike while charging the c in capacitor during acquisition. during conversion, the analog inputs draw only a small leakage current. input voltage (v) 0v output code 236416 f02 111...111 111...110111...101 111...100 000...001 000...000 000...010 000...011 1 lsb unipolarzero fs ? 1lsb 1lsb = fs/65536 r on 40 c in 45pf r on 40 ref ref c in 45pf in + in C bias voltage 236416 f03 downloaded from: http:///
ltc236 4 -16 11 236416fa applications information input drive circuits a low impedance source can directly drive the high im- pedance input of the ltc2364-16 without gain error. a high impedance source should be buffered to minimize settling time during acquisition and to optimize the dis- tortion performance of the adc. minimizing settling time is important even for dc inputs, because the adc input draws a current spike when entering acquisition. for best performance, a buffer amplifier should be used to drive the analog input of the ltc2364-16. the ampli- fier provides low output impedance, which produces fast settling of the analog signal during the acquisition phase. it also provides isolation between the signal source and the current spike the adc input draws.input filtering the noise and distortion of the buffer amplifier and signal source must be considered since they add to the adc noise and distortion. noisy input signals should be filtered prior to the buffer amplifier input with an appropriate filter to minimize noise. the simple 1- pole rc lowpass filter ( lpf1) shown in figure 4 is sufficient for many applications. high quality capacitors and resistors should be used in the rc filters since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems.pseudo-differential unipolar inputs for most applications, we recommend the low power lt6202 adc driver to drive the ltc2364-16. with a low noise density of 1.9 nv/ hz and a low supply current of 3ma, the lt6202 is flexible and may be configured to convert signals of various amplitudes to the 0 v to 5 v input range of the ltc2364-16.to achieve the full distortion performance of the ltc2364 -16, a low distortion single-ended signal source driven through the lt6202 configured as a unity-gain buffer as shown in figure 4 can be used to get the full data sheet thd specification of C120db. the lt6202 can also be used to buffer and convert large true bipolar signals which swing below ground to the 0 v to 5 v input range of the ltc2364-16. figure 5 a shows the lt6202 being used to convert a 10 v true bipolar signal for use by the ltc2364-16. in this case, the lt6202 is configured as an inverting amplifier stage, which acts to attenuate and level shift the input signal to the 0 v to 5 v input range of the ltc2364-16. in the inverting configuration, the single-ended input signal source no longer directly drives a high impedance input . the input impedance is instead set by resistor r in . r in must be chosen carefully based on the source impedance of the signal source. higher values of r in tend to degrade both the noise and distortion of the lt6202 and ltc2364-16 as a system. table 1 shows the resulting snr and thd for several values of r in , r1, r2, r3 and r4 in this configuration. figure 5 b shows the resulting fft when using the lt6202 as shown in figure 5 a. figure 4. input signal chain another filter network consisting of lpf2 should be used between the buffer and adc input to both minimize the noise contribution of the buffer and to help minimize distur - bances reflected into the buffer from sampling transients. long rc time constants at the analog inputs will slow down the settling of the analog inputs. therefore, lpf2 requires a wider bandwidth than lpf1. a buffer amplifier with a low noise density must be selected to minimize degradation of the snr. 10 10nf 66nf 50 lpf2 lpf1 bw = 1.6mhz bw = 48khz ltc2364-16 in + in C 236416 f04 C + lt6202 v ref 0v downloaded from: http:///
ltc236 4 -16 12 236416fa table 1. snr, thd vs r in for 10v input signal r in () r1 () r2 () r3 () r4 () snr (db) thd (db) 2k 499 499 2k 402 94.6 C99.2 10k 2.49k 2.49k 10k 2k 94.4 C93.8 100k 24.9k 24.9k 100k 20k 92.4 C93.7 applications information adc reference the ltc2364-16 requires an external reference to define its input range. a low noise, low temperature drift refer- ence is critical to achieving the full data sheet performance of the adc. linear technology offers a portfolio of high performance references designed to meet the needs of many applications. with its small size, low power and high accuracy, the ltc6655-5 is particularly well suited for use with the ltc2364-16. the ltc6655-5 offers 0.025% (max) initial accuracy and 2 ppm/c ( max) temperature coefficient for high precision applications. the ltc6655-5 is fully specified over the h-grade temperature range and complements the extended temperature operation of the ltc2364-16 up to 125 c. we recommend bypassing the ltc6655-5 with a 47 f ceramic capacitor ( x5r , 0805 size) close to the ref pin.the ref pin of the ltc2364-16 draws charge ( q conv ) from the 47 f bypass capacitor during each conversion cycle. the reference replenishes this charge with a dc current, i ref = q conv /t cyc . the dc current draw of the ref pin, i ref , depends on the sampling rate and output code. if the ltc2364-16 is used to continuously sample a signal at a constant rate, the ltc6655-5 will keep the deviation of the reference voltage over the entire code span to less than 0.5lsbs. when idling, the ref pin on the ltc2364-16 draws only a small leakage current (< 1 a). in applications where a burst of samples is taken after idling for long periods as shown in figure 6, i ref quickly goes from approximately 0a to a maximum of 0.2 ma at 250 ksps. this step in dc current draw triggers a transient response in the reference that must be considered since any deviation in the refer- ence output voltage will affect the accuracy of the output figure 6. cnv waveform showing burst sampling figure 5a. lt6202 converting a 10v bipolar signal to a 0v to 5v input signal figure 5b. 32k point fft plot with f in = 2khz for circuit shown in figure 5a C + 1 3 4 lt6202 r4 402 r1 499 r in 2k r32k r2499 10f 10v C10v 0v 200pf 200pf v cm = v ref /2 5v0v 236416 f05a cnv idle period idle period 236416 f06 frequency (khz) 0 amplitude (dbfs) C80 C60 C40 125 236416 f05b C100 C120 C160 50 100 25 75 C140 0 C20 snr = 94.6dbthd = C99.2db sinad = 92.2db sfdr = 99.9db downloaded from: http:///
ltc236 4 -16 13 236416fa applications information code. in applications where the transient response of the reference is important, the fast settling ltc6655-5 refer- ence is also recommended. in applications where power management is critical and the external reference may be powered down, it is rec- ommended that ref is kept greater than 2 v in order to guarantee a maximum shutdown current of 140 a . in such applications, a schottky diode can be placed between ref and v dd , as shown in figure 7. the rms amplitude of all other frequency components except the first five harmonics and dc. figure 8 shows that the ltc2364-16 achieves a typical snr of 94.7 db at a 250khz sampling rate with a 2khz input. figure 8. 32k point fft with f in = 2khz of the ltc2364-16 frequency (khz) 0 25 50 75 100 125 C180 amplitude (dbfs) C60 C40 C20C80 C100C120 C140 C160 0 236416 f08 snr = 94.7dbthd = C121db sinad = 94.7db sfdr = 125db ref 236416 f07 ltc2364-16 v dd figure 7. a schottky diode between ref and v dd maintains ref > 2v for applications where the reference may be powered down dynamic performance fast fourier transform ( fft ) techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, the adcs spectral content can be examined for frequen- cies outside the fundamental. the ltc2364-16 provides guaranteed tested limits for both ac distortion and noise measurements. signal-to-noise and distortion ratio (sinad) the signal-to-noise and distortion ratio ( sinad) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the a/d output. the output is band-limited to frequencies from above dc and below half the sampling frequency. figure 8 shows that the ltc2364-16 achieves a typical sinad of 94.7 db at a 250 khz sampling rate with a 2khz input.signal-to-noise ratio (snr) the signal-to-noise ratio ( snr) is the ratio between the rms amplitude of the fundamental input frequency and total harmonic distortion (thd) total harmonic distortion ( thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself . the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency ( f smpl /2). thd is expressed as: thd = 20log v2 2 + v3 2 + v4 2 ++ v n 2 v1 where v1 is the rms amplitude of the fundamental fre- quency and v 2 through v n are the amplitudes of the second through nth harmonics. power considerations the ltc2364-16 provides two power supply pins: the 2.5v power supply ( v dd ), and the digital input/output interface power supply ( ov dd ). the flexible ov dd supply allows the ltc2364-16 to communicate with any digital logic operating between 1.8 v and 5 v, including 2.5 v and 3.3v systems.power supply sequencing the ltc2364-16 does not have any specific power supply sequencing requirements. care should be taken to adhere downloaded from: http:///
ltc236 4 -16 14 236416fa applications information to the maximum voltage relationships described in the absolute maximum ratings section. the ltc2364 -16 has a power-on-reset ( por) circuit that will reset the ltc2364-16 at initial power-up or whenever the power supply voltage drops below 1 v. once the supply voltage re-enters the nominal supply voltage range, the por will reinitialize the adc. no conversions should be initiated until 20 s after a por event to ensure the reinitialization period has ended. any conversions initiated before this time will produce invalid results. timing and control cnv timing the ltc2364-16 conversion is controlled by cnv. a ris- ing edge on cnv will start a conversion and power up the ltc2364-16. once a conversion has been initiated, it cannot be restarted until the conversion is complete. for optimum performance, cnv should be driven by a clean low jitter signal. converter status is indicated by the busy output which remains high while the conversion is in progress. to ensure that no errors occur in the digitized results, any additional transitions on cnv should occur within 40 ns from the start of the conversion or after the conversion has been completed. once the conversion has completed, the ltc2364-16 powers down and begins acquiring the input signal.acquisition a proprietary sampling architecture allows the ltc2364-16 to begin acquiring the input signal for the next conver- sion 527 ns after the start of the current conversion. this extends the acquisition time to 3.460 s, easing settling requirements and allowing the use of extremely low power adc drivers. (refer to the timing diagram.) internal conversion clock the ltc2364-16 has an internal clock that is trimmed to achieve a maximum conversion time of 3s. auto power-down the ltc2364-16 automatically powers down after a conversion has been completed and powers up once a new conversion is initiated on the rising edge of cnv. during power down, data from the last conversion can be clocked out. to minimize power dissipation during power down, disable sdo and turn off sck. the auto power-down feature will reduce the power dissipation of the ltc2364-16 as the sampling frequency is reduced . since power is consumed only during a conversion, the ltc2364-16 remains powered down for a larger fraction of the conversion cycle ( t cyc ) at lower sample rates, thereby reducing the average power dissipation which scales with the sampling rate as shown in figure 9. figure 9. power supply current of the ltc2364-16 versus sampling rate sampling rate (khz) 1 0 power supply current (ma) 0.2 0.4 0.6 0.8 1.2 1.6 1.0 1.4 50 100 150 200 i vdd 236416 f09 250 i ovdd i ref digital interface the ltc2364-16 has a serial digital interface. the flexible ov dd supply allows the ltc2364-16 to communicate with any digital logic operating between 1.8 v and 5 v, including 2.5v and 3.3v systems. the serial output data is clocked out on the sdo pin when an external clock is applied to the sck pin if sdo is enabled . clocking out the data after the conversion will yield the best performance. with a shift clock frequency of at least 20mhz, a 250 ksps throughput is still achieved. the serial output data changes state on the rising edge of sck and can be captured on the falling edge or next rising edge of sck. d15 remains valid till the first rising edge of sck. the serial interface on the ltc2364-16 is simple and straightforward to use . the following sections describe the operation of the ltc2364-16. several modes are provided downloaded from: http:///
ltc236 4 -16 15 236416fa timing diagrams depending on whether a single or multiple adcs share the spi bus or are daisy chained.normal mode, single device when chain = 0, the ltc2364-16 operates in normal mode. in normal mode, rdl/sdi enables or disables the serial data output pin sdo. if rdl/sdi is high, sdo is in high impedance. if rdl/sdi is low, sdo is driven. figure 10 shows a single ltc2364-16 operated in nor- mal mode with chain and rdl/sdi tied to ground. with rdl/sdi grounded, sdo is enabled and the msb(d15) of the new conversion data is available at the falling edge of busy. this is the simplest way to operate the ltc2364-16. figure 10. using a single ltc2364-16 in normal mode cnv ltc2364-16 busy convert irq data in digital host clk sdo sck rdl/sdi chain 236416 f10 convert convert t acq t acq = t cyc C t hold power-down power-down cnv chain = 0 busy sck sdo rdl/sdi = 0 t busylh t dsdobusyl t sck t hsdo t sckh t quiet t sckl t dsdo t conv t cnvh t hold acquire t cyc t cnvl d15 d14 d13 d1 d0 1 2 3 14 15 16 acquire downloaded from: http:///
ltc236 4 -16 16 236416fa timing diagrams figure 11. normal mode with multiple devices sharing cnv, sck and sdo normal mode, multiple devicesfigure 11 shows multiple ltc2364-16 devices operating in normal mode ( chain = 0) sharing cnv, sck and sdo. by sharing cnv, sck and sdo, the number of required signals to operate multiple adcs in parallel is reduced . since sdo is shared, the rdl/sdi input of each adc must be used to allow only one ltc2364-16 to drive sdo at a time in order to avoid bus conflicts . as shown in figure 11, the rdl/sdi inputs idle high and are individually brought low to read data out of each device between conversions . when rdl/sdi is brought low, the msb of the selected device is output onto sdo. rdl b rdl a convert irq data in digital host clk cnv ltc2364-16 sdo a sck rdl/sdi cnv ltc2364-16 sdo b sck rdl/sdi chain busy chain 236416 f11 d15 a sdo sck cnv busy chain = 0 rdl/sdi b rdl/sdi a d15 b d14 b d1 b d0 b d13 b d14 a d13 a d1 a d0 a hi-z hi-z hi-z t en t hsdo t dsdo t dis t sckl t sckh t cnvl 1 2 3 14 15 16 17 18 19 30 31 32 t sck convert convert t quiet t conv t hold t busylh power-down acquire acquire power-down downloaded from: http:///
ltc236 4 -16 17 236416fa timing diagrams chain mode, multiple deviceswhen chain = ov dd , the ltc2364-16 operates in chain mode. in chain mode, sdo is always enabled and rdl/sdi serves as the serial data input pin ( sdi) where daisy-chain data output from another adc can be input . this is useful for applications where hardware constraints may limit the number of lines needed to interface to a large number of converters . figure 12 shows an example with two daisy-chained devices. the msb of converter a will appear at sdo of converter b after 16 sck cycles. the msb of converter a is clocked in at the sdi/rdl pin of converter b on the rising edge of the first sck. figure 12. chain mode timing diagram ov dd convert irq data in digital host clk cnv ltc2364-16 busy sdo b sck rdl/sdi cnv ltc2364-16 sdo a sck rdl/sdi chain ov dd chain 236416 f12 d0 a d1 a d14 a d15 a d13 b d14 b d15 b sdo b sdo a = rdl/sdi b rdl/sdi a = 0 d0 b d1 b d13 a d14 a d15 a d0 a d1 a 1 2 3 14 15 16 17 18 30 31 32 t dsdobusyl t ssdisck t hsdisck t busylh t conv t hold t hsdo t dsdo t sckl t sckh t sckch t cnvl t cyc convert convert sck cnv busy chain = ov dd t quiet power-down power-down acquire acquire downloaded from: http:///
ltc236 4 -16 18 236416fa board layout to obtain the best performance from the ltc2364-16 a printed circuit board is recommended. layout for the printed circuit board ( pcb) should ensure the digital and analog signal lines are separated as much as possible . in particular, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the adc. recommended layoutthe following is an example of a recommended pcb layout . a single solid ground plane is used. bypass capacitors to the supplies are placed as close as possible to the supply pins. low impedance common returns for these bypass capacitors are essential to the low noise operation of the adc. the analog input traces are screened by ground. for more details and information refer to dc1813a, the evaluation kit for the ltc2364-16. partial top silkscreen downloaded from: http:///
ltc236 4 -16 19 236416fa board layout partial layer 1 component side partial layer 2 ground plane downloaded from: http:///
ltc236 4 -16 20 236416fa board layout partial layer 3 pwr plane partial layer 4 bottom layer downloaded from: http:///
ltc236 4 -16 21 236416fa board layout partial schematic of demoboard u6 nc7sz66p5x c13 0.1f 4 1 2 9 cnv sck c2047f 6.3v 0805 c56 0.1f cnv ref gndgnd gnd gnd ref v dd v ref 0.8v ref ov dd sck sdo busy rdl/sdi sdobusy rd ltc2364-16 in C in + 5 4 1314 11 12 b a 5 3 gnd v cc oe +3.3v r549.9 1206 r61k u8nc7sz04p5x u2nc7svu04p5x u20 ltc6655ahms8-5 u3 nl17sz74 u4nc7svu04p5x cnvst_33from cpld clkto cpld c5 0.1f c1 0.1f c11 0.1f shdngnd gnd out_f gnd gnd 9v to 10v 1 23 4 87 6 5 +3.3v +3.3v +3.3v 3 4 2 5 3 4 2 5 c2 0.1f r3 33 r21k r1 33 +3.3v +3.3v 3 1 46 2 87 5 r833 r46? r58 ? c3 0.1f r4 33 c4 0.1f v in out_s gnd v cc clr\ q\ cp q d pr\ 3 4 2 5 +3.3v dc590 detectto cpld +3.3v c58 opt u9nc7sz04p5x c15 0.1f c16 0.1f 3 4 2 5 +3.3v r13 1k r172k r104.99k u724lc025-i/st r114.99k r124.99k c14 0.1f 6 84 236416 bl 57 3 2 1 sclsda array eeprom wpa2 a1 a0 v ss v cc 13 5 7 9 1113 24 6 8 10 12 14 j3 dc590 sdo sck cnv 9v to10v r71k 1016 6 31 157 28 jp6 fs 12 3 hd1x3-100 opt c7 0.1f c610f 6.3v +2.5v c10 0.1f c39 0.01f npo c65 opt 0805 npo r38 opt r35 opt r45? c40 opt npo c910f 6.3v r16 0 r32 10 out1 v + v C v+ 14 Cin1 +in1 3 5 2 r19 0 r31 opt u15 lt6202cs5 r32 0 c4215pf c55 1f v + v C c57 0.1f r9 opt c6110f 6.3v c63 10f 6.3v c43 0.1f r15 opt c18 opt c1710f jp2 cm e7 ext_cm 1 +2.5v 23 v ref/2 ext hd1x3-100 c8 1f c46 1f r40 opt r39 0 12 3 couplingac dc jp1 hd1x3-100 c44 1f c49 opt c4810f 6.3v c47 opt r41 opt c59 1f c60 0.1f 12 3 jp5 hd1x3-100 couplingac dc db16 db17 3937 35 33 31 29 27 25 23 21 19 17 15 13 11 97 5 3 1 db0db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 clkout 1 4038 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 j2 con-edge 40-100 clk in j1 j4 j8 r14 0 a in + a in ? C+ downloaded from: http:///
ltc236 4 -16 22 236416fa package description please refer to http:// www .linear.com/designtools/packaging/ for the most recent package drawings. 3.00 0.10 (2 sides) 4.00 0.10 (2 sides) note:1. drawing proposed to be made variation of version (wged-3) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom viewexposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05typ 3.15 ref 1 8 16 9 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (de16) dfn 0806 rev ? pin 1 notchr = 0.20 or 0.35 45 chamfer 3.30 0.10 1.70 0.05 3.15 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 packageoutline 0.25 0.05 3.30 0.05 0.45 bsc 0.23 0.05 0.45 bsc de package 16-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1732 rev ?) msop (ms16) 1107 rev ? 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C?0.27 (.007 C .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16151413121110 1 2 3 4 5 6 7 8 9 note:1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 C 6 typ detail a detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc 4.039 0.102 (.159 .004) (note 3) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) ms package 16-lead plastic msop (reference ltc dwg # 05-08-1669 rev ?) downloaded from: http:///
ltc236 4 -16 23 236416fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 08/12 corrected resolution from 18-bit to 16-bit in description section 1 downloaded from: http:///
ltc236 4 -16 24 236416fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 0812 rev a ? printed in usa 1 5 2 3 ltc2364-16 in + ref v dd 2.5v in C 10nf 47f 10 r4 402 r1 499 r in 2k r32k r23k 10f 200pf 8v 5v lt6202 v + v C C3v 236416 ta02 v out_s v out_f v in ltc6655-5 5v0v 4 C + 220pf 10v C10v 0v part number description comments adcsltc2379-18/ltc2378-18 ltc2377-18/ltc2376-18 18-bit, 1.6msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, differential input, 101.2db snr, 5v input range, dgc, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2380-16/ltc2378-16 ltc2377-16/ltc2376-16 16-bit, 2msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, differential input, 96.2db snr, 5v input range, dgc, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2383-16/ltc2382-16/ltc2381-16 16-bit, 1msps/500ksps/250ksps serial, low power adc 2.5v supply, differential input, 92db snr, 2.5v input range, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2393-16/ltc2392-16/ltc2391-16 16-bit, 1msps/500ksps/250ksps parallel/serial adc 5v supply, differential input, 94db snr, 4.096v input range, pin- compatible family in 7mm 7mm lqfp-48 and qfn-48 packages ltc1864/ltc1864l 16-bit, 250ksps/150ksps 1-channel power adc 5v/3v supply, 1-channel, 4.3mw/1.5mw, msop-8 package ltc1865/ltc1865l 16-bit, 250ksps/150ksps 2-channel power adc 5v/3v supply, 2-channel, 4.3mw/1.3mw, msop-10 package dacs ltc2757 18-bit, single parallel i out softspan? dac 1lsb inl/dnl, software-selectable ranges, 7mm 7mm lqfp-48 package ltc2641 16-bit/14-bit/12-bit single serial v out dacs 1lsb inl/dnl, msop-8, 3mm 3mm dfn, so-8 packages, 0v to 5v output ltc2630 12-bit/10-bit/8-bit single v out dacs sc70 6-pin package, internal reference, 1lsb inl (12 bits) references ltc6655 precision low drift low noise buffered reference 5v/2.5v, 2ppm/c, 0.25ppm peak-to-peak noise, msop-8 package ltc6652 precision low drift low noise buffered reference 5v/2.5v, 5ppm/c, 2.1ppm peak-to-peak noise, msop-8 package amplifiers lt6202/lt6203 single/dual 100mhz rail-to-rail input/output noise low power amplifiers 1.9nv hz , 3ma maximum, 100mhz gain bandwidth lt6200/lt6200-5/ lt6200-10 165mhz/800mhz/1.6ghz op amp with unity gain/ av = 5/ av = 10 low noise voltage: 0.95nv/ hz (100khz), low distortion: C80db at 1mhz, tsot23-6, so-8 packages related parts typical application lt6202 converting a 10v bipolar signal to a 0v to 5v input signal into the ltc2364-16 downloaded from: http:///

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